1. Field of the Invention
The present invention generally relates to computer-aided design and in particular to a hierarchical layout method for integrated circuits.
2. Description of the Related Art
All integrated circuits and their physical packaging are described by physical designs in the form of hierarchical two-dimensional geometric models. Hierarchical characterization is typically used to define the wiring channels and connection ports that can be used to route wire over a design partition in the higher level cell. The complexity of these designs quadruples every couple of years. This increasing data volume is becoming a significant problem for engineering design automation, since it stresses software design systems which in turn impact the design cycle time, design cost and time to market.
The input to the physical design problem is a circuit diagram, and the output is generating a layout of the integrated circuit. Well-known techniques for implementing a physical design include a combination of steps that include partitioning, floor planning, routing, compaction, parasitic extraction, and proper timing in an iterative sequence to form a design process commonly known as the top-down design methodology. The output of partitioning is a set of blocks, along with the interconnections required between blocks. The set of interconnections required is referred to as a xe2x80x9cnetlist,xe2x80x9d which is a compilation of information descriptive of the primitives (i.e., circuit elements) of a logic circuit. xe2x80x9cNetlistxe2x80x9d can also be a cell description (a group of circuit elements) and their interconnection.
Present electronic design systems consist of software tools running on a digital computer that assist a designer in the creation and verification of complex electronic designs. Electronic computer-aided design (ECAD) systems are widely used in designing semiconductor integrated circuits. In particular, ECAD systems are used to generate data descriptive of the entire circuit layout as well as the layout of individual circuit cells. Since each cell often contains a large number of circuit elements and interconnections among the elements, ECAD systems have become an indispensable tool in the design of integrated circuits. In addition to generating layout design, some types of ECAD systems generate mask pattern data using circuit layout data. Mask pattern data is used to control various exposure processes necessary for the integrated circuit""s manufacture.
Known techniques for generation of layouts of integrated circuits include: a) manual layout; b) hierarchical standard-cell with general place/route method, which requires pre-existing layouts for each of the devices; and c) parameterized leaf-cell with general place/route method, which generates the cells. The latter two methods are xe2x80x9cschematic-drivenxe2x80x9d in that the leaf-cells of the layout correspond to a single node in the schematic netlist. In each of these methods, the resulting components (hierarchically structured layouts) are located and wired using an ECAD system for placement and routing of wiring to complete the connections indicated in the netlist.
However, these hierarchically structured layouts are generated for preliminary analysis of the IC layout placement, and not as a final IC layout placement that is typically generated automatically prior to the optional routing and compacting processing. To illustrate this problem, a designer typically xe2x80x9cexplodesxe2x80x9d the logic elements used in a circuit, and examines a direct transistor-level netlist. As such, current placement layout methods require either manual layout which requires a great increase in effort relative to automated placement or generation of individual transistor layouts. Such manual modification is labor intensive and error prone. Use of a general placement present problems that include transistors being larger in size. Also, it is more difficult to achieve an optimal design with general placement since automated transistor design tools are not as sophisticated as standard-cell based tools. Further, there are other method or technical constraints posed by the general placement layout (e.g., embedded latches or SRAM cells are typically selected from a pre-existing library, rather than use of custom cells). In summary, the above problems in connection with current placement layout methodologies are costly and time consuming.
A primary object of the present invention is to provide a method for applying a set of schematic sub-graph recognition rules, (e.g., pattern matching rules, logical analysis) to create an intermediate xe2x80x9crenestedxe2x80x9d schematic to direct a layout generation system during design of an IC chip. In the invention, the term xe2x80x9crenestxe2x80x9d is equivalent in meaning to xe2x80x9cnestingxe2x80x9d depending upon whether preliminary designs are used prior to providing a structured netlist for the layout generation system. The invention allows for the transforming of a flat schematic into a nested (e.g. hierarchical) schematic to provide automatic generation of a layout without the need for manual intervention, yielding optimized context-sensitive of layouts (i.e., a differentiation of occurrences of the same cells in the netlist) of assembled IC components.
Generation of a parameterized pattern library include steps of initially selecting a list of applicable layout generators (e.g, type of topological design element such as a NOR gate, NAND gate or inverter cells). For each selected layout generator, a schematic pattern is created describing a rule for generating a netlist for a specific instance of the layout. The pattern includes a netlist topology and parameters for the nodes (e.g., transistors) of the netlist that are calculated as mathematical expressions of the parameters for that generator. From this pattern, a matching criteria and parameter derivation rules are calculated. The pattern recognition for this generator includes the required topology with matching criteria. Finally, the step of xe2x80x9crenestingxe2x80x9d the netlist includes substituting a recognized topological subgraph with a node representing the layout generator, with parameters as calculated by the parameter derivation rules (when the topological subgraph match the requisite topology and pass the matching criteria).
Another object of the invention is to provide a computer implementation of the method for hierarchical layout of an electronic design, wherein the method includes creating a parameterized pattern library that includes layout generators of elements forming part of the design, followed by inputting a netlist into a pattern recognizer using the parameterized pattern library. Next, a list of associations is created between the parameterized pattern library and the netlist using the pattern recognizer. Then the netlist is renested using the list of associations resulting in generating a hierarchical layout of the electronic components.
Renesting the schematic netlist by the pattern recognizer by initially creating a parameterized pattern library of the components used enables greater productivity in layout generation when compared to conventional manual transistor-level layout. The invention also facilitates in revisions of the layout that frequently occur in response to functional or performance tuning where iterations of preliminary designs are necessary. In addition, the invention aids the eventual migration of a design to subsequent generation of VLSI technology (e.g., from a 0.25 xcexcm process to a 0.18 xcexcm process).